IS42S32200C1-7TL

Product Summary

The IS42S32200C1-7TL is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits. The IS42S32200C1-7TL includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The IS42S32200C1-7TL has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.

Parametrics

IS42S32200C1-7TL absolute maximum ratings: (1)Maximum Supply Voltage:–1.0V to +4.6V; (2)Maximum Supply Voltage for Output Buffer:–1.0V to +4.6V; (3)Input Voltage:–1.0V to +4.6V; (4)Output Voltage:–1.0V to +4.6V; (5)Allowable Power Dissipation:1W; (6)Output Shorted Current:50mA; (7)Operating Temperature: Com.:0℃ to +70℃, Ind.:–40℃ to +85℃; (8)Storage Temperature:–55℃ to +150℃.

Features

IS42S32200C1-7TL features: (1)Clock frequency: 183, 166, 143 MHz; (2)Fully synchronous; all signals referenced to a positive clock edge; (3)Internal bank for hiding row access/precharge; (4)Single 3.3V power supply; (5)LVTTL interface; (6)Programmable burst length:(1, 2, 4, 8, full page); (7)Programmable burst sequence:Sequential/Interleave; (8)Self refresh modes; (9)4096 refresh cycles every 64 ms; (10)Random column address every clock cycle; (11)Programmable CAS latency (2, 3 clocks); (12)Burst read/write and burst read/single write operations capability; (13)Burst termination by burst stop and precharge command; (14)Available in Industrial temperature grade; (15)Available in 400-mil 86-pin TSOP II and 90-ball BGA; (16)Available in Lead free.

Diagrams